System-on-chip for artificial neural network being operated according to dynamically calibrated phase of clock signal

ABSTRACT

A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of Korean Patent Application No. 10-2023-0114904 filed on Aug. 30, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE DISCLOSURE Technical Field

The present disclosure relates to a technique for lowering instantaneous power consumption of a system-on-chip (SoC) for an artificial neural network.

Background Art

Artificial intelligence (AI) is rapidly advancing. AI refers to artificially imitating human intelligence, that is, intelligence capable of recognition, classification, inference, prediction, control/decision making, and the like.

In recent times, to enhance the computational speed for artificial intelligence (AI), a neural processing unit (NPU) has been developed.

Depending on the specific AI service requirements, different types of artificial neural network (ANN) models may exist. For instance, when processing an image or video, a CNN type artificial neural network model can be employed for tasks like object classification, object detection, object tracking, and the like.

Generally, each layer of an artificial neural network model involves varying levels of computation.

In particular, when a specific layer requires a significant increase in computational operations, it can lead to an instantaneous surge in power consumption.

SUMMARY OF THE DISCLOSURE

Artificial neural network operation has a data-intensive characteristic. In particular, artificial neural network calculations require parallel processing calculations. In other words, the artificial neural network operation has a characteristic in that the processing speed is lowered if a large amount of data cannot be processed in parallel at a high speed at the same time.

Accordingly, the inventors of the present disclosure developed a neural processing unit specialized for artificial neural network calculation. The inventors of the present disclosure have attempted to improve the parallel processing performance of the neural processing unit by increasing the number of a plurality of processing elements of the neural processing unit. In addition, the inventors of the present disclosure have attempted to develop a neural processing unit capable of low-power operation.

Meanwhile, a power supply unit of a neural processing unit specialized for low-power operation installed in an edge device may have relatively low power supply capability compared to a power supply unit of a graphic processing unit (GPU) operating in a server or personal computer (PC). In addition, capacitance of a power supply unit of a neural processing unit specialized for low-power operation installed in an edge device may be insufficient to handle peak power supply.

However, the inventors of the present disclosure have recognized that as the number of processing elements of the neural processing unit specialized for low-power operation increases, the degree of instantaneously fluctuating supply voltage may increase. In other words, the required amount of instantaneous power supply of the neural processing unit may be proportional to the number of operating processing elements. In addition, the amount of computation of the artificial neural network model varies considerably for each layer. Therefore, the number of processing elements operating in parallel may be different according to the amount of computation of the layer of the artificial neural network model. That is, when many processing elements operate at the same time, the voltage of the power supply unit of the neural processing unit may fluctuate or drop instantaneously.

In addition, when the supply voltage fluctuates or drops instantaneously, there may be a case in which the supply voltage VDD needs to be raised for system stability. Therefore, if system safety is not secured, a problem in which the supply voltage is unnecessarily increased may occur. When the supply voltage increases, power consumption of the neural processing unit may rapidly increase.

Conversely, as the supply voltage becomes more stable, a level of the supply voltage VDD can be reduced. Therefore, if the stability of the supply voltage of the neural processing unit is ensured, the supply voltage can be reduced, and consequently, the power consumption of the neural processing unit can be reduced.

Accordingly, the inventors of the present disclosure recognized that it is necessary to improve the stability of a supply voltage of a neural processing unit specialized in artificial neural network operation even when the number of processing elements increases.

Accordingly, the disclosures in the present disclosure are aimed at disclosing technical solutions for stabilizing the fluctuation of the supply voltage of the supply power unit due to excessive peak power.

According to an example of the present disclosure, a system-on-chip (SoC) is provided. The SoC may comprise a semiconductor substrate, a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model, a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model, and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals. Each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator. The one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal. A first clock signal among the one or more clock signals may be applied to the first NPU according to the control signal. A second clock signal among the one or more clock signals may be applied to the second NPU according to the control signal.

The SoC may comprise a power management integrated circuit, disposed on the semiconductor substrate, configured to measure power.

The first clock signal or the second clock signal may be delayed in phase by a preset amount compared to the phase of the original clock signal.

The SoC may further comprise a fifth circuitry, disposed on the semiconductor substrate, configured to generate the one or more clock signals including the original clock signal and the one or more phase-delayed clock signals, based on the control signal.

The fifth circuitry may comprise one or more phase shifters connected in series, wherein the one or more phase shifters include a first phase shifter configured to receive the original clock signal, and a selector, connected to the one or more phase shifters, configured to select at least one clock signal among the original clock signal and one or more outputs of the one or more phase shifters.

The first circuitry for the first NPU and the second circuitry for the second NPU may be configured to generate one or more phase-delayed clock signals based on the original clock signal according to the control signal.

A phase of the one or more phase-delayed clock signals may be dynamically adjusted so as to reduce at least one measured power among the first NPU and the second NPU.

When a utilization rate of the first NPU or the second NPU is predicted to be increased, a phase of the one or more phase-delayed clock signals may be shifted or drifted compared to the phase of the original clock signal.

The first clock signal may have a first phase. The second clock signal may have a second phase delayed from the first phase.

A phase of the first clock signal may be identical to the phase of the original clock signal. A phase of the second clock signal may be delayed from the phase of the first clock signal.

According to another example of the present disclosure, a system is provided. The system may comprise a substrate, a first semiconductor chip, mounted on the substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model, a second semiconductor chip, mounted on the substrate, provided for a second NPU configured to perform operations of an ANN model, and a third semiconductor chip, mounted on the substrate, configured to generate a control signal to selectively output one or more clock signals. Each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator. The one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal. A first clock signal among the one or more clock signals may be applied to the first NPU according to the control signal. A second clock signal among the one or more clock signals may be applied to the second NPU according to the control signal.

The system may comprise a power management integrated circuit disposed on the substrate and configured to measure power.

The first clock signal or the second clock signal may be delayed in phase by a preset amount compared to the phase of the original clock signal.

The system may further comprise a fifth semiconductor chip, mounted on the substrate, configured to generate the one or more clock signals including the original clock signal and the one or more phase-delayed clock signals, based on the control signal.

The fifth semiconductor chip may comprise one or more phase shifters connected in series, wherein the one or more phase shifters include a first phase shifter configured to receive the original clock signal, and a selector, connected to the one or more phase shifters, configured to select at least one clock signal among the original clock signal and one or more outputs of the one or more phase shifters.

The first semiconductor chip for the first NPU and the second semiconductor chip for the second NPU may be configured to generate one or more phase-delayed clock signals based on the original clock signal according to the control signal.

A phase of the one or more phase-delayed clock signals may be dynamically adjusted so as to reduce at least one measured power among the first NPU and the second NPU.

When a utilization rate of the first NPU or the second NPU is predicted to be increased, a phase of the one or more phase-delayed clock signals may be shifted or drifted compared to the phase of the original clock signal.

The first clock signal may have a first phase. The second clock signal may have a second phase delayed from the first phase.

A phase of the first clock signal may be identical to the phase of the original clock signal. A phase of the second clock signal may be delayed from the phase of the first clock signal.

According to examples of the present disclosure, an artificial neural network operation is performed in a distributed manner according to a plurality of clock signals, thereby reducing peak power.

According to examples of the present disclosure, an artificial neural network operation is performed in a distributed manner according to a plurality of clock signals, thereby improving the stability of a supply voltage supplied to a neural processing unit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic conceptual diagram illustrating an exemplary artificial neural network model.

FIG. 2A is a diagram for explaining the basic structure of a convolutional neural network (CNN).

FIG. 2B is a comprehensive diagram illustrating the operation of a convolutional neural network.

FIG. 3 is a schematic conceptual diagram illustrating a neural processing unit according to an example of the present disclosure.

FIG. 4A is a schematic conceptual diagram illustrating one processing element among a plurality of processing elements that may be applied to an example of the present disclosure.

FIG. 4B is a schematic conceptual diagram illustrating an SFU that can be applied to an example of the present disclosure.

FIG. 5 is an exemplary diagram illustrating a modified example of the neural processing unit 100 shown in FIG. 3 .

FIG. 6A is an exemplary view illustrating the size of data for each layer in the exemplary artificial neural network model.

FIG. 6B is an exemplary table illustrating the size of data for each layer in the exemplary artificial neural network model shown in FIG. 6A.

FIG. 7A is an exemplary diagram illustrating the structure of a SoC according to an example of the present disclosure.

FIG. 7B is an exemplary diagram briefly illustrating the SoC shown in FIG. 7A.

FIG. 7C is a diagram illustrating the clock source 170 shown in FIG. 7A or 7B in detail according to an example.

FIG. 7D is an exemplary diagram illustrating a plurality of clock signals output by the clock source 170.

FIG. 8A is an exemplary diagram illustrating the structure of an SoC according to another example of the present disclosure.

FIG. 8B is an exemplary diagram illustrating in detail an NPU among the NPUs shown in FIG. 8A.

FIG. 9 illustrates an example in which clock signals of different phases are not input to a plurality of NPUs.

FIG. 10 illustrates an example of inputting clock signals of different phases to four NPUs in consideration of peak power according to an example of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENT

Specific structural or step-by-step descriptions for the embodiments according to the concept of the present disclosure disclosed in the present disclosure or application are merely illustrative for the purpose of describing the embodiments according to the concept of the present disclosure. The examples according to the concept of the present disclosure may be carried out in various forms and are not interpreted as that the present disclosure is limited to the examples described in the present disclosure or application.

Various modifications and changes may be applied to the examples in accordance with the concept of the present disclosure and the examples may have various forms so that the examples will be described in detail in the specification or the application with reference to the drawings. However, it should be understood that the examples according to the concept of the present disclosure is not limited to the specific examples, but includes all changes, equivalents, or alternatives which are in line with the spirit and technical scope of the present disclosure.

Terminologies such as first and/or second may be used to describe various components but the components are not limited by the above terminologies. The above terminologies are used to distinguish one component from the other component, for example, a first component may be referred to as a second component without departing from a scope in accordance with the concept of the present invention and similarly, a second component may be referred to as a first component.

It should be understood that, when it is described that an element is “coupled” or “connected” to another element, the element may be directly coupled or directly connected to the other element or coupled or connected to the other element through a third element. In contrast, when it is described that an element is “directly coupled” or “directly connected” to another element, it should be understood that no element is present therebetween. Other expressions which describe the relationship between components, for example, “between,” “adjacent to,” and “directly adjacent to” should be interpreted in the same manner.

Terminologies used in the present disclosure are used only to describe specific examples, and are not intended to limit the present disclosure. A singular form may include a plural form if there is no clearly opposite meaning in the context. In the present disclosure, it should be understood that terms “include” or “have” indicate that a feature, a number, a step, an operation, a component, a part, or a combination thereof described in the present disclosure is present, but do not exclude a possibility of presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof, in advance.

If it is not contrarily defined, all terms used herein including technological or scientific terms have the same meaning as those generally understood by a person with ordinary skill in the art. Terminologies which are defined in a generally used dictionary should be interpreted to have the same meaning as the meaning in the context of the related art but are not interpreted as an ideally or excessively formal meaning if it is not clearly defined in the present disclosure.

In describing examples, descriptions of technical contents that are well known in the art to which the present disclosure pertains and are not directly related to the present disclosure will be omitted. The omission is to convey the gist of the present disclosure more clearly without the obscuration of the unnecessary description of well-known technical details.

Definitions of Terms

Here, in order to help the understanding of the examples proposed in the present disclosure, terminologies used in the present disclosure will be defined in brief.

NPU is an abbreviation for a neural processing unit and refers to a processor specialized for an operation of an artificial neural network model separately from the central processor (CPU).

ANN is an abbreviation for an artificial neural network and refers to a network which connects nodes in a layered structure by imitating the connection of the neurons in the human brain through a synapse to imitate the human intelligence.

DNN is an abbreviation for a deep neural network and may mean that the number of hidden layers of the artificial neural network is increased to implement higher artificial intelligence.

CNN is an abbreviation for a convolutional neural network and is a neural network which functions similar to the image processing performed in a visual cortex of the human brain. The convolutional neural network is known to be appropriate for image processing and is known to be easy to extract features of input data and identify the pattern of the features.

Hereinafter, the present disclosure will be described in detail by explaining examples of the present disclosure with reference to the accompanying drawings.

Artificial Intelligence

Humans are equipped with intelligence capable of recognition, classification, inference, prediction, control/decision making, and the like. Artificial intelligence (AI) refers to the artificial imitation of human intelligence.

The human brain consists of numerous nerve cells called neurons. Each neuron is connected to hundreds to thousands of other neurons through connections called synapses. In order to imitate human intelligence, modeling the operating principle of biological neurons and the connection between neurons is called an artificial neural network model. In other words, an artificial neural network is a system in which nodes that imitate neurons are connected in a layer structure.

These artificial neural network models are divided into ‘single-layer neural networks’ and ‘multi-layer neural network’ according to the number of layers. A typical multi-layer neural network consists of an input layer, a hidden layer, and an output layer. (1) The input layer is a layer that receives external data, and the number of neurons in the input layer is the same as the number of input variables. (2) The hidden layer is located between the input layer and the output layer, receives signals from the input layer, extracts characteristics, and transfers them to the output layer. (3) The output layer receives signals from the hidden layer and outputs the result. The input signal between neurons is multiplied by each connection weight having a value between 0 and 1 and summed. If this sum is greater than the neuron's threshold, the neuron is activated and implemented as an output value through an activation function.

Meanwhile, in order to implement higher artificial intelligence, an artificial neural network in which the number of hidden layers is increased is called a deep neural network (DNN).

DNNs are being developed in various structures. For example, a convolutional neural network (CNN), which is an example of DNN, is known to be easy to extract features of an input value (video or image) and identify a pattern of the extracted output value. A CNN may be configured in a form in which a convolution operation, an activation function operation, a pooling operation, and the like are processed in a specific order.

For example, in each layer of the DNN, parameters (i.e., input values, output values, weights or kernels, and the like) may be a matrix composed of a plurality of channels. Parameters can be processed in the NPU by convolution or matrix multiplication. In each layer, an output value that has been processed is generated.

For example, a transformer is a DNN based on attention technology. Transformers utilize a number of matrix multiplication operations. The transformer may obtain an output value of attention (Q, K, V) by using parameters such as an input value and a query (Q), a key (K), and a value (V). The transformer can process various inference operations based on the output value (i.e., attention (Q, K, V)). Transformers tend to show better inference performance than CNNs.

FIG. 1 illustrates an exemplary artificial neural network model.

Hereinafter, an operation of an exemplary artificial neural network model 110 a which may operate in the neural processing unit 100 will be explained.

The exemplary artificial neural network model 110 a of FIG. 1 may be an artificial neural network trained to perform various inference functions such as object detection or voice recognition.

The artificial neural network model 110 a may be a deep neural network (DNN).

However, the artificial neural network model 110 a according to the examples of the present disclosure is not limited to the deep neural network.

For example, the artificial neural network model can be a model such as ViT, DaViT, MobileViT, S win-Transformer, Transformer, YOLO (You Only Look Once), CNN, PIDNet, BiseNet, RCNN, VGG, VGG16, DenseNet, SegNet, DeconvNet, DeepLAB V3+, U-net, SqueezeNet, Alexnet, ResNet18, MobileNet-v2, GoogLeNet, Resnet-v2, Resnet50, Resnet101, Inception-v3, and the like. However, the artificial neural network model 110 a may be an ensemble model based on at least two different models.

Hereinafter, an inference process by the exemplary artificial neural network model 110 a will be described.

The artificial neural network model 110 a may be an exemplary deep neural network model including an input layer 110 a-1, a first connection network 110 a-2, a first hidden layer 110 a-3, a second connection network 110 a-4, a second hidden layer 110 a-5, a third connection network 110 a-6, and an output layer 110 a-7. However, the present disclosure is not limited only to the artificial neural network model illustrated in FIG. 1 . The first hidden layer 110 a-3 and the second hidden layer 110 a-5 may also be referred to as a plurality of hidden layers.

The input layer 110 a-1 may exemplarily include input nodes x1 and x2. That is, the input layer 110 a-1 may include information about two input values.

For example, the first connection network 110 a-2 may include information about six weight values for connecting nodes of the input layer 110 a-1 to nodes of the first hidden layer 110 a-3, respectively. Each weight value is multiplied with the input node value, and an accumulated value of the multiplied values is stored in the first hidden layer 110 a-3. Here, the nodes and weights may be referred to as parameters.

For example, the first hidden layer 110 a-3 may include nodes a1, a2, and a3. That is, the first hidden layer 110 a-3 may include information about three node values.

The first processing element PE1 of FIG. 1 may perform the MAC operation of the a1 node.

The second processing element PE2 of FIG. 1 may perform the MAC operation of the a2 node.

The third processing element PE3 of FIG. 1 may perform the MAC operation of the a3 node.

For example, the second connection network 110 a-4 may include information about nine weight values for connecting nodes of the first hidden layer 110 a-3 to nodes of the second hidden layer 110 a-5, respectively. The weight value of the second connection network 110 a-4 is multiplied with the node value input from the corresponding first hidden layer 110 a-3 and the accumulated value of the multiplied values is stored in the second hidden layer 110 a-5.

For example, the second hidden layer 110 a-5 may include nodes b1, b2, and b3. That is, the second hidden layer 110 a-5 may include information about three node values.

The fourth processing element PE4 of FIG. 1 may process the operation of the b1 node.

The fifth processing element PE5 of FIG. 1 may process the operation of node b2.

The sixth processing element PE6 of FIG. 1 may process the operation of node b3.

For example, the third connection network 110 a-6 may include information about six weight values which connect nodes of the second hidden layer 110 a-5 and nodes of the output layer 110 a-7, respectively. The weight value of the third connection network 110 a-6 is multiplied with the node value input from the second hidden layer 110 a-5, and the accumulated value of the multiplied values is stored in the output layer 110 a-7.

For example, the output layer 110 a-7 may include nodes y1 and y2. That is, the output layer 110 a-7 may include information about two node values.

The seventh processing element PE7 of FIG. 1 may process the operation of node y1.

The eighth processing element PE8 of FIG. 1 may process the operation of node y2.

Each node may correspond to a feature value, and the feature value may correspond to a feature map.

FIG. 2A is a diagram for explaining the basic structure of a convolutional neural network (CNN).

Referring to FIG. 2A, an input image may be displayed as a two-dimensional matrix composed of rows of a specific size and columns of a specific size. An input image may have a plurality of channels, where the channels may represent the number of color components of the input data image.

The convolution process means performing a convolution operation with a kernel while traversing the input image at specified intervals.

A convolutional neural network may have a structure in which an output value (convolution or matrix multiplication) of a current layer is transferred as an input value of a next layer.

For example, convolution is defined by two main parameters (input feature map and kernel). Parameters may include input feature maps, output feature maps, activation maps, weights, kernels, attention (Q, K, V) values, and the like.

Convolution slides the kernel window over the input feature map. The step size by which the kernel slides over the input feature map is called the stride.

After convolution, pooling may be applied. In addition, a fully-connected (FC) layer may be disposed at an end of the convolutional neural network.

FIG. 2B is a comprehensive diagram illustrating the operation of a convolutional neural network.

Referring to FIG. 2B, an input image is exemplarily represented as a two-dimensional matrix having a size of 6×6. In addition, FIG. 2B exemplarily illustrates three nodes, channel 1, channel 2, and channel 3.

First, the convolution operation will be described.

The input image (shown as an example of size 6×6 in FIG. 2B) is convolved with a kernel 1 (shown as an example of size 3×3 in FIG. 2B) for channel 1 at the first node, resulting in the output feature map 1 (shown as an example of size 4×4 in FIG. 2B). Similarly, the input image (shown as an example of size 6×6 in FIG. 2B) is convolved with a kernel 2 (shown as an example of size 3×3 in FIG. 2B) for channel 2 at the second node, resulting in the output feature map 2 (shown as an example of size 4×4 in FIG. 2B). Additionally, the input image is convolved with a kernel 3 (shown as an example of size 3×3 in FIG. 2B) for channel 3 at the third node, resulting in the output feature map 3 (shown as an example of size 4×4 in FIG. 2B).

To process each convolution, the processing elements PE1 to PE12 of the neural processing unit 100 are configured to perform a MAC operation.

Next, the operation of the activation function will be described.

The feature map 1, the feature map 2, and the feature map 3 (which are represented as 4×4 examples in FIG. 2B) generated from convolutional operations can be subjected to activation functions. The output after the activation function is applied may have a size of 4×4, for example.

Next, a pooling operation will be described.

Feature map 1, feature map 2, and feature map 3 output from the activation function (each size is exemplarily represented as 4×4 in FIG. 2B) are input to three nodes. Pooling may be performed by receiving feature maps output from the activation function as inputs. The pooling may reduce the size or emphasize a specific value in the matrix. Pooling methods include maximum pooling, average pooling, and minimum pooling. Maximum pooling is used to collect the maximum values in a specific region of the matrix, and average pooling can be used to find the average within a specific region.

In the example of FIG. 2B, it is shown that a feature map having a size of 4×4 is reduced to a size of 2×2 by pooling.

Specifically, the first node receives feature map 1 for channel 1 as an input, performs pooling, and outputs, for example, a 2×2 matrix. The second node receives feature map 2 for channel 2 as an input, performs pooling, and outputs, for example, a 2×2 matrix. The third node receives feature map 3 for channel 3 as an input, performs pooling, and outputs, for example, a 2×2 matrix.

The aforementioned convolution, activation function, and pooling are repeated, and finally, it can be output as fully connected. The corresponding output may be input again to an artificial neural network for image recognition. However, the present disclosure is not limited to the sizes of feature maps and kernels.

The CNN described so far is the most used method in the field of computer vision among various deep neural network (DNN) methods. In particular, CNNs have shown remarkable performance in various research areas performing various tasks such as image classification and object detection.

Required Hardware Resources for ANN

FIG. 3 is a schematic conceptual diagram illustrating a neural processing unit according to the present disclosure.

Referring to FIG. 3 , a neural processing unit (NPU) 100 is a processor specialized to perform an operation for an artificial neural network.

The artificial neural network refers to a network that consists of artificial neurons which, when receiving various inputs or entry stimulations, multiply a weight by the inputs or stimulations, add the multiplied values, and convert a value obtained by additionally adding a deviation using an active function to transmit. The artificial neural network trained as described above may be used to output an inference result from input data.

The neural processing unit 100 may be a semiconductor device implemented by an electric/electronic circuit. The electric/electronic circuit may refer to a circuit including a large number of electronic elements (transistors, capacitors, and the like).

In the case of a transformer and/or CNN-based artificial neural network model, the neural processing unit 100 may select and process matrix multiplication operations, convolution operations, and the like according to the architecture of the artificial neural network.

For example, in each layer of a convolutional neural network (CNN), an input feature map corresponding to input data and a kernel corresponding to weights may be a tensor or matrix composed of a plurality of channels. A convolution operation between the input feature map and the kernel is performed, and a convolution operation and a pooled output feature map are generated in each channel. An activation map of a corresponding channel is generated by applying an activation function to the output feature map. After that, pooling for the activation map may be applied. Here, the activation map may be collectively referred to as an output feature map. For convenience of explanation, the activation map may be referred to as an output feature map.

However, examples of the present disclosure are not limited thereto, and the output feature map means that a matrix multiplication operation or a convolution operation is applied.

To elaborate, the output feature map according to the examples of the present disclosure should be interpreted in a comprehensive sense. For example, the output feature map may be a result of a matrix multiplication operation or a convolution operation. Accordingly, the plurality of processing elements 110 may be modified to further include processing circuitry for processing additional algorithms. That is, some circuit units of the SFU 150 to be described later may be configured to be included in the plurality of processing elements 110.

The neural processing unit 100 may be configured to include a plurality of processing elements 110 for processing convolution and matrix multiplication necessary for the above-described artificial neural network operation.

The neural processing unit 100 may be configured to include each processing circuit optimized for matrix-multiplication operation, convolution operation, activation function operation, pooling operation, stride operation, batch-normalization operation, skip-connection operation, concatenation operation, quantization operation, clipping operation, padding operation, and the like required for the above-described artificial neural network operation.

For example, the neural processing unit 100 may be configured to include the SFU 150 for processing at least one of activation function operation, pooling operation, stride operation, batch-normalization operation, skip-connection operation, concatenation operation, quantization operation, clipping operation, and padding operation for the above-described algorithms.

The neural processing unit 100 may include a plurality of processing elements (PE) 110, an NPU internal memory 120, an NPU controller 130, and an NPU interface 140. Each of the plurality of processing elements 110, the NPU internal memory 120, the NPU controller 130, and the NPU interface 140 may be a semiconductor circuit to which a large number of the electronic elements are connected. Therefore, some of electronic elements may be difficult to identify or be distinguished with the naked eye, but may be identified only by a circuitry operation.

For example, an arbitrary circuit may operate as a plurality of the processing elements 110, or may operate as an NPU controller 130. The NPU controller 130 may be configured to perform the function of the control unit that is configured to control the artificial neural network inference operation of the neural processing unit 100.

The neural processing unit 100 may include an NPU controller 130 including an NPU internal memory 120 configured to store parameters of an artificial neural network model that can be inferred from the plurality of processing elements 110 and the SFU 150 and a scheduler configured to control operation schedules of the plurality of processing elements 110, the SFU 150, and the NPU internal memory 120.

The neural processing unit 100 may be configured to process the feature map corresponding to the encoding and decoding method using scalable video coding (SVC) or scalable feature-map coding (SFC). The above schemes are technologies that variably vary the data transmission rate according to the effective bandwidth and signal to noise ratio (SNR) of a communication channel or communication bus. That is, the neural processing unit 100 may be configured to further include an encoder and a decoder.

The plurality of processing elements 110 may perform a portion of the operations for an artificial neural network.

SFU 150 may perform another portion of the operation for the artificial neural network.

The neural processing unit 100 may be configured to hardware-accelerate the computation of the artificial neural network model using the plurality of processing elements 110 and the SFU 150.

The NPU interface 140 may communicate with various components connected to the neural processing unit 100, for example, memories, via a system bus.

The NPU controller 130 may include a scheduler configured to control the operation of multiple processing elements 110 for inference operations of a neural processing unit 100, as well as operations of the SFU 150 and reading and writing order of the internal memory 120 of the NPU.

The scheduler in the NPU controller 130 may be configured to control the plurality of processing elements 110, the SFU 150, and the NPU internal memory 120 based on data locality information or structure information of the artificial neural network model.

The schedular in the NPU controller 130 may analyze or receive analyzed information on a structure of an artificial neural network model which may operate in the plurality of processing elements 110. The analyzed information may be information generated by a compiler. For example, data of the artificial neural network, which may be included in the artificial neural network model may include node data (i.e., feature map) of each layer, data on a layout of layers, locality information of layers or information about the structure, and at least a portion of weight data (i.e., weight kernel) of each of connection networks connecting the nodes of the layers. The data of the artificial neural network may be stored in a memory provided in the NPU controller 130 or the NPU internal memory 120. However, it is not limited thereto, and the data of the artificial neural network may be stored in a separate cache memory or register file provided in the NPU or SoC including the NPU.

The scheduler in the NPU controller 130 may receive scheduling information of an operation sequence of the artificial neural network model to be performed by the neural processing unit 100 based on data locality information or structure information of the compiled artificial neural network model. For example, the scheduling information may be information generated by a compiler. Scheduling information generated by the compiler may be referred to as machine code or binary code.

That is, the scheduling information utilized by the NPU controller 130 may be information generated by a compiler based on data locality information or structure of an artificial neural network model.

In other words, the compiler can efficiently schedule NPUs depending on how well the compiler understands and reconstructs the locality of artificial neural network data, which is a unique characteristic of artificial neural network models.

In other words, the compiler can efficiently schedule the NPU according to how well the compiler understands the hardware structure and performance of the neural processing unit 100.

In other words, when the artificial neural network model is compiled to be executed in the neural processing unit 100 by the compiler, the artificial neural network data locality may be reconstructed. The artificial neural network data locality can be reconstructed according to the algorithms applied to the artificial neural network model and the operating characteristics of the processor.

To elaborate, the artificial neural network data locality can be reconstructed according to a method in which the neural processing unit 100 processes the corresponding artificial neural network model, for example, feature map tiling or a stationary method of processing elements.

To elaborate, artificial neural network data locality can be reconstructed according to the number of processing elements of the neural processing unit 100 and the capacity of the internal memory.

To elaborate, the artificial neural network data locality can be reconstructed according to the bandwidth of the memory communicating with the neural processing unit 100.

This is because the neural processing unit 100 may differently determine the order of necessary data at each moment in each clock cycle even though the same artificial neural network model is operated and processed by each of the factors described above.

Based on the order of data required for the operation of the artificial neural network model, the compiler may determine data locality and generate compiled machine code based on the order of operation of the layers, convolutions and/or matrix multiplications of the artificial neural network.

The scheduler may be configured to utilize scheduling information contained in machine code. The scheduler in the NPU controller 130 may obtain a memory address value in which the feature map and weight data of the layer of the artificial neural network model are stored based on the scheduling information.

For example, the scheduler in the NPU controller 130 may acquire the memory address value of the feature map of the layer of the artificial neural network model and the weight data which are stored in the memory. Accordingly, the scheduler in the NPU controller 130 may acquire feature map of a layer and weight data of an artificial neural network model to be driven from the main memory, to store the acquired data in the NPU internal memory 120.

Feature map of each layer may have a corresponding memory address value.

Each of the weight data may have a corresponding memory address value.

The scheduler in the NPU controller 130 may schedule an operation order of the plurality of processing elements 110 based on the data locality information or the information about the structure of the artificial neural network model, for example, the layout information of layers of the artificial neural network or the information about the structure of the artificial neural network model.

The scheduler in the NPU controller 130 may schedule based on the data locality information or the information about the structure of the artificial neural network model so that the NPU scheduler may operate in a different way from a scheduling concept of a normal CPU. The scheduling of the normal CPU operates to provide the highest efficiency in consideration of fairness, efficiency, stability, and reaction time. That is, the normal CPU schedules to perform the most processing during the same time in consideration of a priority and an operation time.

A conventional CPU uses an algorithm which schedules a task in consideration of data such as a priority or an operation processing time of each processing.

In contrast, the scheduler in the NPU controller 130 may control the neural processing unit 100 according to a determined processing order of the neural processing unit 100 based on the data locality information or the information about the structure of the artificial neural network model.

Moreover, the scheduler in the NPU controller 130 may operate the neural processing unit 100 according to the determined the processing order based on the data locality information or the information about the structure of the artificial neural network model and/or data locality information or information about a structure of the neural processing unit 100 to be used.

However, the present disclosure is not limited to the data locality information or the information about the structure of the neural processing unit 100.

The scheduler in the NPU controller 130 may be configured to store the data locality information or the information about the structure of the artificial neural network.

That is, even though only the data locality information or the information about the structure of the artificial neural network of the artificial neural network model is utilized, the scheduler in the NPU controller 130 may determine a processing sequence.

Moreover, the scheduler in NPU controller 130 may determine the processing order of the neural processing unit 100 by considering the data locality information or the information about the structure of the artificial neural network model and data locality information or information about a structure of the neural processing unit 100. Furthermore, it is possible to optimize the processing according to the determined processing order.

That is, the NPU controller 130 may be configured to operate based on machine code compiled by a compiler, but in another example, the NPU controller 130 may be configured to embed an embedded compiler. According to the above-described configuration, the neural processing unit 100 may be configured to receive a file in the form of a framework of various AI software and generate machine code. For example, AI software frameworks may include TensorFlow, PyTorch, Keras, XGBoost, mxnet, DARKNET, ONNX, and the like.

The plurality of processing elements 110 refers to a configuration in which a plurality of processing elements PE1 to PE12 that is configured to operate feature map and weight data of the artificial neural network is deployed. Each processing element may include a multiply and accumulate (MAC) operator and/or an arithmetic logic unit (ALU) operator, but the examples according to the present disclosure are not limited thereto.

Each processing element may further include an additional special function unit for processing the additional special functions.

For example, it is also possible for the processing element PE to be modified and implemented to further include a batch-normalization unit, an activation function unit, an interpolation unit, and the like.

The SFU 150 may include each processing circuit configured to select and process activation function operation, pooling operation, stride operation, batch-normalization operation, skip-connection operation, concatenation operation, quantization operation, clipping operation, padding operation, and the like according to the architecture of the artificial neural network. That is, the SFU 150 may include a plurality of special function arithmetic processing circuit units.

Even though FIG. 3 illustrates a plurality of processing elements as an example, operators implemented by a plurality of multiplier and adder trees may also be configured to be deployed in parallel in one processing element, instead of the MAC. In this case, the plurality of processing elements 110 may also be referred to as at least one processing element including a plurality of operators.

The plurality of processing elements 110 is configured to include a plurality of processing elements PE1 to PE12. The plurality of processing elements PE1 to PE12 of FIG. 5 is merely an example for the convenience of description and the number of the plurality of processing elements PE1 to PE12 is not limited to 12 or any other integer numbers. A size or the number of processing element arrays 110 may be determined by the number of the plurality of processing elements PE1 to PE12. The size of the plurality of processing elements 110 may be implemented by an N×M matrix. Here, N and M are integers greater than zero. The plurality of processing elements 110 may include N×M processing elements. That is, one or more processing elements may be provided.

A number of the plurality of processing elements 110 may be designed in consideration of the characteristic of the artificial neural network model in which the neural processing unit 100 operates.

The plurality of processing elements 110 is configured to perform a function such as addition, multiplication, and accumulation required for the artificial neural network operation. In other words, the plurality of processing elements 110 may be configured to perform a multiplication and accumulation (MAC) operation.

Hereinafter, a first processing element PE1 among the plurality of processing elements 110 will be explained with an example.

FIG. 4A illustrates one processing element among a plurality of processing elements that may be applied to the present disclosure.

As illustrated in FIG. 3 , the neural processing unit 100 according to the examples of the present disclosure may include the plurality of processing elements 110, the NPU internal memory 120 configured to store an artificial neural network model inferred from the plurality of processing elements 110, and the NPU controller 130 configured to control the plurality of processing elements 110 and the NPU internal memory 120 based on data locality information or information about a structure of the artificial neural network model. The plurality of processing elements 110 is configured to perform the MAC operation and the plurality of processing elements 110 is configured to quantize and output the MAC operation result, but the examples of the present disclosure are not limited thereto.

The NPU internal memory 120 may store all or a part of the artificial neural network model in accordance with the memory size and the data size of the artificial neural network model.

As illustrated in FIG. 4A, the first processing element PE1 may include a multiplier 111, an adder 112, an accumulator 113, and a bit quantizer 114. However, the examples according to the present disclosure are not limited thereto and the plurality of processing elements 110 may be modified in consideration of the operation characteristic of the artificial neural network.

The multiplier 111 multiplies input (N) bit data and (M) bit data. The operation value of the multiplier 111 is output as (N+M) bit data.

The multiplier 111 may be configured to receive one variable and one constant.

The accumulator 113 accumulates an operation value of the multiplier 111 and an operation value of the accumulator 113 using the adder 112 as many times as the number of (L) loops. Therefore, a bit width of data of an output unit and an input unit of the accumulator 113 may be output to (N+M+log 2(L)) bits. Here, L is an integer greater than zero.

When the accumulation is completed, the accumulator 113 is applied with an initialization reset to initialize the data stored in the accumulator 113 to zero, but the examples according to the present disclosure are not limited thereto.

The bit quantizer 114 may reduce the bit width of the data output from the accumulator 113. The bit quantizer 114 may be controlled by the NPU controller 130. The bit width of the quantized data may be output to (X) bits. Here, X is an integer greater than zero. According to the above-described configuration, the plurality of processing elements 110 is configured to perform the MAC operation and the plurality of processing elements 110 may quantize the MAC operation result to output the result. The quantization may have an effect that the larger the (L) loops, the smaller the power consumption. Further, when the power consumption is reduced, the heat generation may also be reduced. Additionally, when the heat generation is reduced, the possibility of the erroneous operation of the neural processing unit 100 due to the high temperature may be reduced.

Output data (X) bits of the bit quantizer 114 may serve as node data of a subsequent layer or input data of a convolution. When the artificial neural network model is quantized, the bit quantizer 114 may be configured to be supplied with quantized information from the artificial neural network model. However, it is not limited thereto and the NPU controller 130 may also be configured to extract quantized information by analyzing the artificial neural network model. Accordingly, the output data (X) bit is converted to a quantized bit width to be output so as to correspond to the quantized data size. The output data (X) bit of the bit quantizer 114 may be stored in the NPU internal memory 120 with a quantized bit width.

The plurality of processing elements 110 of the neural processing unit 100 according to an example of the present disclosure may include a multiplier 111, an adder 112, and an accumulator 113. The bit quantizer 114 may be selected according to whether quantization is applied or not. In another example, the bit quantization unit may also be configured to be included in the SFU 150.

FIG. 4B is a schematic conceptual diagram illustrating an SFU that can be applied to the present disclosure.

Referring to FIG. 4B, the SFU 150 may include several functional units. Each functional unit can be operated selectively. Each functional unit can be selectively turned on or turned off. That is, each functional unit can be set.

In other words, the SFU 150 may include various circuit units required for an artificial neural network inference operation.

For example, the circuit units of the SFU 150 may include a functional unit for skip-connection operation, a functional unit for activation function operation, a functional unit for pooling operation, a functional unit for quantization operation, a functional unit for non-maximum suppression (NMS) operation, a functional unit for integer to floating point conversion (INT to FP32) operation, a functional unit for a batch-normalization operation, a functional unit for an interpolation operation, a functional unit for a concatenation operation, a functional unit for a bias operation, and the like.

Functional units of the SFU 150 may be selectively turned on or off according to the data locality information of the artificial neural network model. Data locality information of an artificial neural network model may include turn-off of a corresponding functional unit or control information related to turn-off when an operation for a specific layer is performed.

An activated unit among functional units of the SFU 150 may be turned on. In this way, when some functional units of the SFU 150 are selectively turned off, power consumption of the neural processing unit 100 can be reduced. Meanwhile, in order to turn off some functional units, power gating may be used. Alternatively, clock gating may be performed to turn off some functional units.

FIG. 5 illustrates a modified example of the neural processing unit 100 of FIG. 3 .

The neural processing unit 100 of FIG. 5 is substantially the same as the neural processing unit 100 exemplarily illustrated in FIG. 3 , except for the shown addition of the plurality of processing elements 110. Thus, redundant description will be omitted for the brevity.

The plurality of processing elements 110 exemplarily illustrated in FIG. 5 may further include register files RF1 to RF12, each of which corresponds to processing elements PE1 to PE12 respectively, in addition to a plurality of processing elements PE1 to PE12.

The plurality of processing elements PE1 to PE12 and the plurality of register files RF1 to RF12 of FIG. 5 are merely an example for the convenience of description and the number of the plurality of processing elements PE1 to PE12 and the plurality of register files RF1 to RF12 is not limited to 12 or any other integer number.

A size of, or the number of, processing element arrays 110 may be determined by the number of the plurality of processing elements PE1 to PE12 and the plurality of register files RF1 to RF12. The size of the plurality of processing elements 110 and the plurality of register files RF1 to RF12 may be implemented by an N×M matrix. Here, N and M are integers greater than zero.

An array size of the plurality of processing elements 110 may be designed in consideration of the characteristic of the artificial neural network model in which the neural processing unit 100 operates. For additional explanation, the memory size of the register file may be determined in consideration of a data size, a required operating speed, and a required power consumption of the artificial neural network model to operate.

The register files RF1 to RF12 of the neural processing unit 100 are static memory units which are directly connected to the processing elements PE1 to PE12. For example, the register files RF1 to RF12 may be configured by flip-flops and/or latches. The register files RF1 to RF12 may be configured to store the MAC operation value of the corresponding processing elements PE1 to PE12. The register files RF1 to RF12 may be configured to provide or be provided with the weight data and/or node data to or from the NPU internal memory 120.

It is also possible that the register files RF1 to RF12 are configured to perform a function of a temporary memory of the accumulator during MAC operation.

Technical Difficulties Found by the Inventors of the Present Disclosure

Depending on the purpose of the artificial intelligence service, several types of artificial neural network (ANN) models may exist. For example, when input data is an image or video, a CNN type artificial neural network model for object classification, object detection, object tracking, and the like in an image/video may be used for artificial intelligence service.

In general, an artificial neural network model may have a different amount of computation for each layer. This will be described with reference to FIGS. 6A and 6B.

FIG. 6A is an exemplary view illustrating the size of data for each layer in the exemplary artificial neural network model, and FIG. 6B is an exemplary table illustrating the size of data for each layer in the exemplary artificial neural network model shown in FIG. 6A.

The exemplary artificial neural network model shown in FIG. 6A is shown to be Mobilenet V 1. The horizontal axis shown in FIG. 6A represents layers sequentially in the exemplary artificial neural network model, and the vertical axis represents the size of data.

Referring to layer 1 shown in FIG. 6A, it can be seen that the size of the output feature map OFMAP_SIZE is greater than the size of the input feature map IFMAP_SIZE.

The output feature map of the first layer is transferred to the second layer and becomes the input feature map of the second layer. When the calculation of the second layer is completed, an output feature map is output. The output feature map of the second layer is transferred to the third layer again, and becomes the input feature map of the third layer.

As such, the size of input data input to each layer and the size of an output feature map output from each layer may be different. Accordingly, the amount of calculation may be small in a certain layer, but the amount of calculation may be very large in another layer. In this way, as the amount of computation per layer is greatly fluctuated, a problem of managing power stability may occur.

The amount of computation of each layer can be known by MAC. It can be seen that the amount of computation for each layer differs by a maximum of 227 times.

The neural network processing unit 100 may determine the number of operating processing elements among the plurality of processing elements 110 in proportion to the MAC operation amount for each layer. In addition, power consumption may increase in proportion to the number of operating processing elements.

In addition, as the difference in MAC computation amount between adjacent layers increases, the deviation of peak power between adjacent layers may increase. Also, the larger the deviation of the peak power, the more the supply voltage VDD (e.g., a driving voltage) may fluctuate.

In particular, the inventors of the present disclosure have recognized that when the amount of calculations greatly increases in a specific layer, peak power consumption increases, thereby deteriorating system stability.

For example, many processing elements may be operated at the same time for the operation of a specific layer. A certain amount of power is required to drive each processing element, and when a considerable number of processing elements are simultaneously driven, the required power may rapidly increase. If the neural processing unit is designed specifically for low-power operation, the power supply capability may be relatively less than that of the neural processing unit for a server. Accordingly, such a neural processing unit for an edge device may be relatively more vulnerable to an instantaneous power supply issue, and a supply voltage VDD may fluctuate when the power supply amount increases exponentially. Thus, data stored in the transistor may be lost, especially if the supply voltage VDD drops below the threshold voltage of the transistor. In other words, when the supply voltage VDD is lowered, setup/hold violation problems may occur in the neural processing unit, resulting in malfunction.

For another example, the inventors of the present disclosure have recognized that since the plurality of PEs 110 that perform operations for an artificial neural network, for example, add, multiply, and accumulate instantaneously consume a lot of power, sufficient power may not be supplied to other components in the NPU, for example, the internal memory 120. Specifically, the inventors of the present disclosure have recognized that there may be a problem that cannot be ruled out that, if sufficient power is not supplied to the internal memory 120, the possibility of compromising stored data bits may occur.

Disclosures of the Present Disclosure

The inventors of the present disclosure have recognized that the above-mentioned problem may be occurred due to a clock signal supplied to a hardware for performing calculations of the artificial neural network model.

Accordingly, the inventors of the present disclosure have invented a technique to lower peak power by allowing a plurality of NPUs to operate according to different clock signals.

Various examples in which the technique invented by the inventors of the present disclosure is implemented will be described below with reference to the drawings.

FIG. 7A is an exemplary diagram illustrating the structure of an SoC according to an example of the present disclosure, and FIG. 7B is an exemplary diagram illustrating the SoC shown in FIG. 7A.

Referring to FIGS. 7A and 7B, the example SoC 1000 may include a plurality of NPUs, a plurality of central processing units (CPUs), and a plurality of memories.

Referring to FIGS. 7A and 7B, the plurality of NPUs may include, for example, a first NPU 100-1, a second NPU 100-2, a third NPU 100-3, and a fourth NPU 100-4.

Referring to FIG. 7A, the plurality of CPUs may include, for example, a first CPU 200-1 and a second CPU 200-2. The plurality of memories may include a first memory 300-1 and a second memory 300-2. In FIG. 7A, the number of CPUs and memories is shown as two each, but the number is not limited thereto and the number may be variously modified to four, six, eight and the like.

Each of the plurality of NPUs 100-1, 100-2, 100-3, and 100-4 shown in FIGS. 7A and 7B may include PEs 110, an internal memory 120, an NPU controller 130, an NPU interface 140, and SFU 150 as shown in FIG. 3 or FIG. 5 .

Referring to FIG. 7A, the exemplary SoC 1000 may include a memory controller 350, a system bus 500, and an input output (I/O) interface 800.

The system bus 500 may be implemented by an electrically conductive pattern formed on a semiconductor substrate. The system bus enables high-speed communication. For example, the plurality of NPUs, the plurality of CPUs, the plurality of memories, and the memory controller 350 may communicate with each other through the system bus 500.

The plurality of NPUs and the plurality of CPUs may request the memory controller 350 through the system bus 500 to read or write data from at least one of the plurality of memories.

Meanwhile, referring to FIGS. 7A and 7B, the exemplary SoC 1000 may include a clock source 170 and a phase determination circuit 190. A power management integrated circuit (PMIC) 180 may be connected to the phase determination circuit 190. The PMIC 180 is shown as being disposed outside the SoC 1000 in FIGS. 7A and 7B, but is not limited thereto. Depending on implementation, the PMIC 180 may be integrated within the SoC 1000 or within a package including the SoC 1000. That is, the SoC 1000 and the PMIC 180 can be integrated in a system in package (SiP). Alternatively, the SoC 1000 and the PMIC 180 may be integrated in a chip on wafer on substrate (CoWoS).

Each the plurality of NPUs 100-1, 100-2, 100-3, and 100-4, the plurality of CPUs 200-1 and 200-2, the plurality of memories 300-1 and 300-2, the clock source 170, and the phase determination circuit 190 in the SoC 1000 may be a semiconductor circuit with numerous transistors connected. Therefore, some of them may be difficult to identify and distinguish with the naked eye, and can only be identified through operation thereof.

The clock source 170 may be a circuit configured to output one or more clock signals. The clock source 170 may include a clock signal generation circuit 171 and a phase shifter 175 as shown in FIG. 7C, which will be described later.

The PMIC 180 may be a circuit configured to measure the power of the SoC 1000 or the power of each of the plurality of NPUs. Here, the power may be measured differently depending on the utilization rate of the plurality of NPUs. In other words, the measured power may be affected by the utilization rate of plurality of NPUs.

To reduce peak power of the plurality of NPUs or the SoC, the phase determination circuit 190 may generate a control signal to calibrate or adjust at least one phase of the one or more clock signals to be output by the clock source 170 based on the power measured by the PMIC 180 and transmit the control signal to the clock source 170.

The phase shifter 175 in the clock source 170 may bypass the original clock signal and output it, or may delay or shift the phase of the original clock signal and output it according to the control signal from the phase determination circuit 190.

Specifically, the phase shifter 175 in the clock source 170 may dynamically adjust and output at least one phase of the one or more clock signals so that the measured power is lower than the peak power. At least one phase of the one or more clock signals may be adjusted based on the utilization rate of any NPU among the plurality of NPUs.

For example, if the utilization rate of any NPU among the plurality of NPUs is predicted to be higher than before, the phase shifter 175 within the clock source 170 may output a phase-delayed clock signal in which the phase of the original clock signal is shifted or drifted according to the control signal from the phase determination circuit 190 so as to reduce the peak power.

In more details, the phase shifter 175 in the clock source 170 may transmit the original clock signal generated by the clock signal generation circuit 171 to the first NPU 100-1 by bypassing or may transmit a first delayed clock signal that delays or shifts the phase of the original clock signal to the second NPU 100-2 according to the control signal from the phase determination circuit 190. In addition, the phase shifter 175 may transmit a second delayed clock signal that delays or shifts the phase of the original clock signal generated by the clock signal generation circuit 171 to the third NPU 100-3 according to the control signal from the phase determination circuit 190.

FIG. 7C is an exemplary diagram illustrating the clock source 170 shown in FIG. 7A or FIG. 7B in detail according to an example of the present disclosure, and FIG. 7D is an exemplary diagram illustrating a plurality of clock signals output by the clock source 170.

As shown in FIG. 7C, the clock source 170 may include a clock signal generation circuit 171 and a phase shifter 175.

The clock signal generation circuit 171 may include an oscillator. Additionally, the oscillator may include a pulse width modulator (PWM) circuit. The PWM can adjust the ratio of high and low signals by changing the duty cycle of the clock cycle.

The phase shifter 175 may include a plurality of shifters S and a multiplexer/selector 175-5. In FIG. 7C, it is shown that there are four shifters 175-1, 175-2, 175-3, and 175-4.

Hereinafter, the description will be made with reference to FIGS. 7C and 7D.

The original clock signal output from the clock signal generation circuit 171 may be bypassed within the phase shifter 175 and output through the multiplexer/selector 175-5.

In addition, the original clock signal output from the clock signal generation circuit 171, shifted into a first delayed clock signal by delaying the phase once through the first shifter 175-1 in the phase shifter 175, can be output through the multiplexer/selector 175-5.

In addition, the original clock signal output from the clock signal generation circuit 171 is shifted into a third delayed clock signal by delaying the phase three times through the first shifter 175-1, second shifter 175-2, and third shifter 175-3 in the phase shifter 175, and the third delayed clock signal may be output through the multiplexer/selector 175-5.

As shown in FIG. 7C, according to the control signal from the phase determination circuit 190, the multiplexer/selector 175-5 may multiplex a plurality of clock signals (e.g., the original clock signal, the first delayed clock signal, the second delayed clock signal, the third delayed clock signal, and the fourth delayed clock signal) and then selectively provide one clock signal to each of the plurality of NPUs.

For example, according to the control signal from the phase determination circuit 190, the multiplexer/selector 175-5 may provide the original clock signal to the first NPU 100-1, the first delayed clock signal to the second NPU 100-2, the second delayed clock signal to the third NPU 100-3, and the third delayed clock signal to the third NPU 100-4. In this way, by operating a plurality of NPUs according to various clock signals with different phases, a sudden increase in peak power can be suppressed.

According to an example of the present disclosure, as described above, by simply adding a phase shifter 175 in order to provide a plurality of clock signals with different phases instead of having a plurality of clock sources 170, the manufacturing cost can be reduced.

FIG. 8A is an exemplary diagram illustrating the structure of an SoC according to another example of the present disclosure, and FIG. 8B is an exemplary diagram illustrating in detail an NPU among the NPUs shown in FIG. 8A.

Referring to FIG. 8A, the exemplary SoC 1000 may include a plurality of NPUs, a clock source 170, and a phase determination circuit 190. A power measurement integrated circuit (PMIC) 180 may be connected to the phase determination circuit 190. A power management integrated circuit (PMIC) 180 may be connected to the phase determination circuit 190. The PMIC 180 is shown in FIG. 8A as being disposed outside the SoC 1000, but is not limited thereto. Depending on implementation, the PMIC 180 may be integrated within the SoC 1000 or within a package including the SoC 1000. That is, the SoC 1000 and the PMIC 180 can be integrated in a system in package (SiP). Alternatively, the SoC 1000 and the PMIC 180 may be integrated in a chip on wafer on substrate (CoWoS).

The plurality of NPUs may include, for example, a first NPU 100-1, a second NPU 100-2, a third NPU 100-3, and a fourth NPU 100-4.

Each of the plurality of NPUs 100-1, 100-2, 100-3, and 100-4, the clock source 170, and the phase determination circuit 190 in the SoC 1000 may be a semiconductor circuit to which numerous transistors are connected. Therefore, some of them may be difficult to identify and distinguish with the naked eye, and can only be identified through movement.

The SoC 1000 as shown in FIG. 8A may further include a plurality of CPUs 200-1 and 200-2, a plurality of memories 300-1 and 300-2, a memory controller 350, a system bus 500, and an input output (I/O) interface as shown in FIG. 7A.

Each of the plurality of NPUs 100-1, 100-2, 100-3, and 100-4 as shown in FIG. 8A may include PEs 110, an internal memory 120, an NPU controller 130, an NPU interface 140, and a SFU 150 as shown in FIG. 3 or FIG. 5 .

In addition, each of the plurality of NPUs 100-1, 100-2, 100-3, and 100-4 may further include a phase shifter 175 as shown in FIGS. 8A and 8B. That is, unlike what is shown in FIG. 7A, in FIGS. 8A and 8B the phase shifter 175 is shown as being included in each NPU.

The clock source 170 may be a circuit set to output one original clock signal.

The PMIC 180 may be a circuit configured to measure the power of the SoC 1000 or the power of each of the plurality of NPUs. Here, the power may be measured differently depending on the utilization rate of the plurality of NPUs.

The phase determination circuit 190 may generate a control signal for allowing the phase shifter 175 to calibrate or adjust the phase of the original clock signal output from the clock source 170 and output to the phase shifter 175 based on the power measured by the PMIC 180 so as to reduce peak power of the plurality of NPUs or the SoC.

According to the control signal from the phase determination circuit 190, the phase shifter 175 within each NPU may bypass the original clock signal and output it, or delay or shift the phase of the original clock signal and then output it.

Referring to FIG. 8B in detail, the phase shifter 175 may include a plurality of shifters S and a selector 175-5. In FIG. 8B, it is shown that there are four shifters 175-1, 175-2, 175-3, and 175-4.

The original clock signal received from the clock signal generation circuit 171 is bypassed within the phase shifter 175 and transmitted to the selector 175-5.

The original clock signal received from the clock signal generation circuit 171 is shifted into a first delayed clock signal by delaying its phase once through the first shifter 175-1 in the phase shifter 175, and is then transmitted to the selector 175-5.

In addition, the original clock signal received from the clock signal generation circuit 171 is shifted into a second delayed clock signal by delaying its phase twice through the first shifter 175-1 and the second shifter 175-2 in the phase shifter 175 and then transmitted to the selector 175-5.

In addition, the original clock signal received from the clock signal generation circuit 171 is shifted into a third delayed clock signal by delaying its phase three times through the first shifter 175-1, the second shifter 175-2, and the third shifter 175-3 in the phase shifter 175 and then transmitted to the selector 175-5.

In addition, the original clock signal received from the clock signal generation circuit 171 is shifted into a fourth delayed clock signal by delaying its phase four times through the first shifter 175-1, the second shifter 175-2, the third shifter 175-3, and the fourth shifter 175-4 in the phase shifter 175 and then transmitted to the selector 175-5.

According to the control signal from the phase determination circuit 190, the selector 175-5 may select one of a plurality of clock signals (i.e., the original clock signal, the first delayed clock signal, the second delayed clock signal, the third delayed clock signal, and the fourth delayed clock signal) and provide the selected clock signal to the NPU controller 130 or the PEs 110.

For example, when the utilization rate of the plurality of NPUs is predicted to be higher than before.

In such case, in order to reduce the peak power, the selector 175-5 in the phase shifter 175 of the first NPU 100-1 may select the first delayed clock signal according to a control signal from the phase determination circuit 190. In addition, the selector 175-5 in the phase shifter 175 of the second NPU 100-2 may select the second delayed clock signal according to the control signal from the phase determination circuit 190. In addition, the selector 175-5 in the phase shifter 175 of the third NPU 100-3 may select the third delayed clock signal according to the control signal from the phase determination circuit 190. Likewise, the selector 175-5 in the phase shifter 175 of the fourth NPU 100-4 may select the fourth delayed clock signal according to the control signal from the phase determination circuit 190.

In this way, by operating a plurality of NPUs according to various clock signals with different phases, a sudden increase in peak power can be suppressed.

That is, according to an example of the present disclosure, the average power or energy used by the SoC can be maintained stable, and the peak power can be reduced.

In addition, according to an example of the present disclosure, in order to provide a plurality of clock signals with different phases, the manufacturing cost can be reduced by simply adding a phase shifter 175 instead of installing a plurality of clock sources 170.

So far, the explanation has been focused on system on chip (SoC), the present disclosure is not limited to SoC, and the content of the present disclosure can also be applied to a system in package (SiP) or printed circuit board (PCB)-based board level system. For example, each functional component may be implemented as an independent semiconductor chip and connected to each other through a system bus implemented by an electrically conductive pattern formed on a PCB.

For example, an electrically conductive pattern serving as the system bus 500 may be formed on a board substrate rather than an SoC. Also, the first semiconductor chip 100-1 provided for the first NPU and the second semiconductor chip 100-2 provided for the second NPU may be mounted on the board substrate. Additionally, a semiconductor chip for the first memory 300-1 and a semiconductor chip for the second memory 300-2 may be mounted on the board substrate. Additionally, a memory controller 350 may be mounted on the board substrate. Additionally, a semiconductor chip for the first CPU 200-1 and a semiconductor chip for the second CPU 200-2 may be mounted on the board. Additionally, a semiconductor chip for the I/O interface 800 may be mounted on the board. The board substrate may be a printed circuit board (PCB).

FIG. 9 illustrates a comparative example in which clock signals of different phases are not input to a plurality of NPUs.

Referring to FIG. 9 , the first clock CLK0 may be input to the first NPU 100-1, the second NPU 100-2, the third NPU 100-3, and the fourth NPU 100-2. Here, the plural neural processing units 100-1, 100-2, 100-3, and 100-4 are configured to receive clock signals of the same phase. The plurality of neural processing units may include the first NPU 100-1, the second NPU 100-2, the third NPU 100-3, and the fourth NPU 100-4.

100× of PE utilization in FIG. 9 exemplarily illustrates peak power and supply voltage VDD fluctuation characteristics when one hundred processing elements are activated.

200× of PE utilization in FIG. 9 exemplarily illustrates peak power and supply voltage VDD fluctuation characteristics when two hundred processing elements are activated.

500× of PE utilization in FIG. 9 exemplarily illustrates peak power and supply voltage VDD fluctuation characteristics when five hundred processing elements are activated.

Referring to FIG. 9 , as the number of activated processing elements of the neural processing unit 100 increases, the peak power increases and the supply voltage VDD tends to fluctuate.

To explain further, the number of PEs operating for each clock cycle may vary depending on the performance of a compiler that compiles an artificial neural network model. That is, the better the performance of the compiler, the more PEs can be operated per one clock cycle. Here, the ratio of operating PEs among all PEs may be referred to as a PE utilization rate (%). Conversely, the higher the performance of the compiler, the higher the peak power of the NPU can be. That is, the peak power may be directly proportional to the operation rate of the PE. Therefore, as the algorithm of the compiler becomes more sophisticated, there is a problem in that the peak power fluctuation of the NPU may further increase.

Referring to FIG. 9 , the peak power of the first NPU 100-1, the second NPU 100-2, the third NPU 100-3, and the fourth NPU 100-4 operating based on the first clock CLK0 may vary depending on the number of PEs operating per one clock cycle. That is, peak power may be increased in proportion to the number of PEs operating at one clock cycle.

To elaborate, the NPU developed with low power platform can be developed to correspond to the M.2 interface or the PCI Express interface when applied to edge devices. In particular, in the case of the M.2 interface, the maximum power may be relatively lower than that of the PCI Express interface. For example, an M.2 interface may have a current limit of 3 A and a power limit of 10 W. If the peak power of the NPU of the comparative example exceeds 10 W at a specific clock cycle, the supply voltage VDD supplied to the NPU may fluctuate. In this case, as the operation rate of the PE increases, the peak power of the NPU further increases, and as the peak power exceeds the power limit, the degree of decrease in the supply voltage VDD may increase in proportion to the degree of exceeding the peak power.

If the supply voltage VDD falls below the IR-drop margin, an error may occur in the data being calculated by the NPU. To explain further, IR-drop can occur when a voltage drop (V=IR) occurs according to Ohm's law, which is caused by the resistance (R) of the metal interconnection and the current (I) flowing through it. When a large number of logic gates associated with multiple PEs of an NPU switch simultaneously, the NPU can consume a significant amount of current. This high current can cause a larger voltage drop across the NPU, reducing the supply voltage in other parts of the SoC.

Summarizing the comparative example of FIG. 9 , a sufficient IR-drop margin must be secured to ensure stable operation of the NPU and prevent potential errors. The IR-drop margin may mean the difference between the supply voltage VDD and the lowest allowable voltage at any point of the NPU under any

FIG. 10 illustrates an example of inputting clock signals of different phases to four NPUs in consideration of peak power according to an example of the present disclosure.

Referring to FIG. 10 , the first clock CLK1 may be input to the first NPU 100-1, the second clock CLK2 may be input to the second NPU 100-2 the third clock CLK3 may be input to the third NPU 100-3, and the fourth clock CLK4 may be input to the third NPU 100-4. Here, the first NPU 100-1, the second NPU 100-2, the third NPU 100-3, and the fourth NPU 100-4 are configured to receive clock signals of different phases.

100× of PE utilization in FIG. 10 exemplarily illustrates peak power and supply voltage VDD fluctuation characteristics when one hundred processing elements are activated.

200× of PE utilization in FIG. 10 exemplarily illustrates peak power and supply voltage VDD fluctuation characteristics when two hundred processing elements are activated.

500× of PE utilization in FIG. 10 exemplarily illustrates peak power and supply voltage VDD fluctuation characteristics when five hundred processing elements are activated.

Referring to FIG. 10 , as the number of activated processing elements of the neural processing unit 100 increases, the peak power increases and the supply voltage VDD tends to decrease. However, as signal clocks having different phases are input to the NPUs, the overall peak power is reduced and the fluctuation of the supply voltage VDD is also reduced.

A first clock CLK1 may be applied to the first NPU 100-1, a second clock CLK2 may be applied to the second NPU 100-2, a third clock CLK3 may be applied to the third NPU 100-3, and a fourth clock CLK4 may be applied to the fourth NPU 100-4.

As shown in FIG. 10 , the section in which the peak power of each NPU occurs can be distributed along the time axis, and the overall peak power can be greatly distributed. In this case, the voltage stability of the supply voltage (VDD) may be relatively more stable compared to the comparative example shown in FIG. 9 .

Brief Summary of Disclosures of the Present Disclosure

A system-on-chip (SoC) may comprise a semiconductor substrate, a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN), a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model, and a third circuitry, disposed on the semiconductor substrate, generating a control signal to selectively output one or more clock signals. Each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator. The one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal. A first clock signal among the one or more clock signals may be applied to the first NPU according to the control signal. A second clock signal among the one or more clock signals may be applied to the second NPU according to the control signal.

The SoC may comprise a power management integrated circuit, disposed on the semiconductor substrate, configured to measure power.

The first clock signal or the second clock signal may be delayed in phase by a preset amount compared to the phase of the original clock signal.

The SoC may comprise a fifth circuitry configured to generate the one or more clock signals including the original clock signal and the one or more phase-delayed clock signals, based on the control signal.

The fifth circuitry may comprise one or more phase shifters connected in series, wherein a first phase shifter among the one or more phase shifters receives the original clock signal, and a selector, inputs the original clock signal and connected to outputs of the one or more phase shifters, selects the original clock signal and one or more outputs of the one or more phase shifters.

The first circuitry for the first NPU and the second circuitry for the second NPU may include a fifth circuitry configured to generate the one or more clock signals including the original clock signal and the one or more phase-delayed clock signals, based on the control signal.

A phase of the one or more phase-delayed clock signals may be dynamically adjusted so as to reduce at least one measured power among the first NPU and the second NPU.

When a utilization rate of the first NPU or the second NPU is predicted to be increased, a phase of the one or more phase-delayed clock signals may be shifted or drifted compared to the phase of the original clock signal.

The first clock signal may have a first phase. The second clock signal may have a second phase delayed from the first phase.

A phase of the first clock signal may be identical to the phase of the original clock signal. A phase of the second clock signal may be delayed from the phase of the first clock signal.

A system may comprise a substrate, a first semiconductor chip, mounted on the substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN), a second semiconductor chip, mounted on the substrate, provided for a second NPU configured to perform operations of an ANN model, and a third semiconductor chip, mounted on the substrate, generating a control signal to selectively output one or more clock signals. Each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator. The one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal. A first clock signal among the one or more clock signals may be applied to the first NPU according to the control signal. A second clock signal among the one or more clock signals may be applied to the second NPU according to the control signal.

The system may comprise a power management integrated circuit disposed on the substrate and configured to measure power.

The first clock signal or the second clock signal may be delayed in phase by a preset amount compared to the phase of the original clock signal.

The system may comprise a fifth circuitry configured to generate the one or more clock signals including the original clock signal and the one or more phase-delayed clock signals, based on the control signal.

The fifth circuitry may comprise one or more phase shifters connected in series, wherein a first phase shifter among the one or more phase shifters receives the original clock signal, and a selector, inputs the original clock signal and connected to outputs of the one or more phase shifters, selects the original clock signal and one or more outputs of the one or more phase shifters.

The first semiconductor chip for the first NPU and the second semiconductor chip for the second NPU may include a fifth circuitry configured to generate the one or more clock signals including the original clock signal and the one or more phase-delayed clock signals, based on the control signal.

A phase of the one or more phase-delayed clock signals may be dynamically adjusted so as to reduce at least one measured power among the first NPU and the second NPU.

When a utilization rate of the first NPU or the second NPU is predicted to be increased, a phase of the one or more phase-delayed clock signals may be shifted or drifted compared to the phase of the original clock signal.

The first clock signal may have a first phase. The second clock signal may have a second phase delayed from the first phase.

A phase of the first clock signal may be identical to the phase of the original clock signal. A phase of the second clock signal may be delayed from the phase of the first clock signal.

Examples of the present disclosure described in the present disclosure and drawings are merely presented as specific examples to easily explain the technical content of the present disclosure and help understanding of the present disclosure, and are not intended to limit the scope of the present disclosure. It is apparent to those of ordinary skill in the art that other modified examples can be implemented or derived in addition to the examples described.

[National R&D Project Supporting This Invention]

-   -   [Task Identification Number] 1711193211     -   [Task Number] 2022-0-00957-002     -   [Name of Ministry] Ministry of Science and ICT     -   [Name of Project Management (Specialized) Institution] Institute         of Information & Communications Technology Planning & Evaluation     -   [Research Project Title] Development of Core Technology for PIM         Artificial Intelligence Semiconductor (Design)     -   [Research Task Title] PIM semiconductor technology development         for distributed edge devices to converge an on-chip memory and a         calculator     -   [Contribution Rate]1/1     -   [Name of Organization Performing the Task] DeepX Co., Ltd.     -   [Research period] 2023-01-01˜2023-12-31 

What is claimed is:
 1. A system-on-chip (SoC) comprising: a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator, wherein the one or more clock signals include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal, wherein a first clock signal among the one or more clock signals is applied to the first NPU according to the control signal, and wherein a second clock signal among the one or more clock signals is applied to the second NPU according to the control signal.
 2. The SoC of claim 1, further comprising a power management integrated circuit disposed on the semiconductor substrate and configured to measure power.
 3. The SoC of claim 1, wherein the first clock signal or the second clock signal is delayed in phase by a preset amount compared to the phase of the original clock signal.
 4. The SoC of claim 1, further comprising: a fifth circuitry, disposed on the semiconductor substrate, configured to generate the one or more clock signals including the original clock signal and the one or more phase-delayed clock signals, based on the control signal.
 5. The SoC of claim 4, wherein the fifth circuitry comprises: one or more phase shifters connected in series, wherein the one or more phase shifters include a first phase shifter configured to receive the original clock signal; and a selector, connected to the one or more phase shifters, configured to select at least one clock signal among the original clock signal and one or more outputs of the one or more phase shifters.
 6. The SoC of claim 1, wherein the first circuitry for the first NPU and the second circuitry for the second NPU are configured to generate one or more phase-delayed clock signals based on the original clock signal according to the control signal.
 7. The SoC of claim 1, wherein a phase of the one or more phase-delayed clock signals is dynamically adjusted so as to reduce at least one measured power among the first NPU and the second NPU.
 8. The SoC of claim 1, wherein when a utilization rate of the first NPU or the second NPU is predicted to be increased, a phase of the one or more phase-delayed clock signals is shifted or drifted compared to the phase of the original clock signal.
 9. The SoC of claim 1, wherein the first clock signal has a first phase, and wherein the second clock signal has a second phase delayed from the first phase.
 10. The SoC of claim 1, wherein a phase of the first clock signal is identical to the phase of the original clock signal, and wherein a phase of the second clock signal is delayed from the phase of the first clock signal.
 11. A system comprising: a substrate; a first semiconductor chip, mounted on the substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second semiconductor chip, mounted on the substrate, provided for a second NPU configured to perform operations of an ANN model; and a third semiconductor chip, mounted on the substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU includes a plurality of processing elements (PEs), and the plurality of PEs include an adder, a multiplier, and an accumulator, wherein the one or more clock signals include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal, wherein a first clock signal among the one or more clock signals is applied to the first NPU according to the control signal, and wherein a second clock signal among the one or more clock signals is applied to the second NPU according to the control signal.
 12. The system of claim 11, further comprising a power management integrated circuit disposed on the substrate and configured to measure power.
 13. The system of claim 11, wherein the first clock signal or the second clock signal is delayed in phase by a preset amount compared to the phase of the original clock signal.
 14. The system of claim 11, further comprising a fifth semiconductor chip, mounted on the substrate, configured to generate the one or more clock signals including the original clock signal and the one or more phase-delayed clock signals, based on the control signal.
 15. The system of claim 14, wherein the fifth semiconductor chip comprises: one or more phase shifters connected in series, wherein the one or more phase shifters include a first phase shifter configured to receive the original clock signal; and a selector, connected to the one or more phase shifters, configured to select at least one clock signal among the original clock signal and one or more outputs of the one or more phase shifters.
 16. The system of claim 11, wherein the first semiconductor chip for the first NPU and the second semiconductor chip for the second NPU are configured to generate one or more phase-delayed clock signals based on the original clock signal according to the control signal.
 17. The system of claim 11, wherein a phase of the one or more phase-delayed clock signals is dynamically adjusted so as to reduce at least one measured power among the first NPU and the second NPU.
 18. The system of claim 11, wherein when a utilization rate of the first NPU or the second NPU is predicted to be increased, a phase of the one or more phase-delayed clock signals is shifted or drifted compared to the phase of the original clock signal.
 19. The system of claim 11, wherein the first clock signal has a first phase, and wherein the second clock signal has a second phase delayed from the first phase.
 20. The system of claim 11, wherein a phase of the first clock signal is identical to the phase of the original clock signal, and wherein a phase of the second clock signal is delayed from the phase of the first clock signal. 